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DRAM-Feature

Last week, JEDEC announced that the upcoming DDR5 retentiveness standard will offer double the bandwidth and density of DDR4, better channel efficiency, and offering meliorate ability efficiency too. The new standard isn't expected to be in-market until 2022 — JEDEC volition finalize the standard side by side year, and announce new details at its Server Forum consequence in Santa Clara.

A new DDR5 retentiveness standard for servers, desktops, and laptops would offer improved bandwidth (at least eventually), though memory latency still always jumps between generations and rarely much surpasses the original standard, even at high frequency. Higher bandwidth is always helpful in server workloads and some workstation applications, and desktops and laptops with integrated graphics e'er benefit from having more memory bandwidth to apply for gaming or 3D applications.

JEDEC also announced that its NVDIMM-P specification standard is also moving along well. Nosotros've talked several times in the past almost the hardware efforts to move NAND — flash memory — into DIMM sockets and data centers. Intel's 3D XPoint retentivity, Optane, is as well designed to fit in DIMM sockets, though the visitor hasn't launched that version notwithstanding.

NVDIMM-P

NVDIMM-P is a new NVDIMM standard and will take its place amid the multiple variants already in-market. NVDIMM-N matches an equal amount of DRAM and NAND flash on the aforementioned DIMM. NVDIMM-F uses a small corporeality of DRAM to buffer a large amount of flash and is typically used as an alternative to a PCI Express SSD. These drives have lower latency and meliorate responsiveness when placed on the DRAM bus instead of the PCIe interface. NVDIMM-P combines NAND and DRAM on a single chip and can interface with two unlike access mechanisms while using the existing DDR4 standard.

Back when DDR4 was new, we discussed some of the future technologies that might replace DRAM in a number of devices, including Hybrid Memory Cube, High Bandwidth Retentiveness, and Samsung's Wide I/O. Of the 3, we've only seen HBM devices in-market, and those just on a relative handful of GPU models. That should alter when AMD launches Vega subsequently this yr, but if JEDEC is planning for a DDR5, it apparently doesn't think these alternate architectures are going to obviate the need for one in the near time to come. If the DDR5 standard is finished in 2022, information technology would likely launch in 2022-2020, but might not go mainstream until 2022-2023. Given how slowly computers evolve these days, information technology seems DRAM volition exist with us in i course or another for the foreseeable futurity.